1. Field of the Invention
The present invention relates to a processor architecture, and more particularly to a processor architecture for resynchronizing operations following certain conditions.
2. Description of the Related Art
Processors and computers generally handle instructions in several steps, usually including steps of fetching, decoding and executing instructions. Early technology processors performed these steps serially. Advances in technology have led to pipelined-architecture processors, also called scalar processors, which perform different steps of many instructions concurrently. A "superscalar" processor is implemented using a pipelined structure, but improves performance by concurrently handling several scalar instructions in each processing step. Accordingly, several instructions are processed at one time in the superscalar processor pipeline.
In a superscalar processor, instruction conflicts and dependency conditions arise in which a dispatched instruction cannot be executed because data or resources are not available. For example, a dispatched instruction cannot execute when its operands are dependent upon data calculated by other nonexecuted instructions. Thus, performance of a superscalar processor is further improved when multiple concurrently-executing instructions are allowed to access a common register. However, this inherently creates a resource conflict. One technique for resolving register conflicts is called "register renaming". Multiple temporary renaming registers are dynamically allocated, one for each instruction that sets a value for a permanent register. In this manner, one permanent register may serve as a destination for receiving the results of multiple instructions. These results are temporarily held in the multiple allocated temporary renaming registers. The processor keeps track of the renaming registers so that an instruction that receives data from a renaming register accesses the appropriate register. This register renaming function may be implemented using a reorder buffer which contains temporary renaming registers.
Superscalar processor performance is further improved by the speculative execution of branching instructions, in which conditions of branching are predicted and instructions are processed based on those predictions so that instructions are continually decoded without waiting for verification of the predictions. Decoupling of instruction decoding and instruction execution employs a buffer between the processor's instruction decoder and functional units that execute instructions.
Thus, in addition to the several instructions that are processed at one time in the superscalar processor pipeline, additional instructions in a speculative state are held in the processor buffer.
Occasionally a condition arises in which it is desirable to terminate instructions in the pipeline and discard results of speculative instructions but to retain results of instructions that are no longer speculative.
What is desired is a processor and method of operating a processor that clears the superscalar pipeline and the speculative state of the processor and restarts instruction processing at the most recent nonspeculative instruction. The nonspeculative state of the processor must be precisely retained.